The Intel® Xeon® processor E5-1600/E5-2600/E5-4600 product families are the next generation of 64-bit, multi-core enterprise
processors built on 32-nanometer process technology. Throughout this document, the Intel® Xeon® processor E5-1600/E5-
2600/E5-4600 product families may be referred to as simply the processor. Where information differs between the EP and EP 4S
SKUs, this document uses specific Intel® Xeon® processor E5-1600 product family, Intel® Xeon® processor E5-2600 product
family, and Intel® Xeon® processor E5-4600 product family notation.Based on the low-power/high performance 2nd Generation
Intel® Core™ Processor Family microarchitecture, the processor is designed for a two chip platform consisting of a processor and a
Platform Controller Hub (PCH) enabling higher performance, easier validation, and improved x-y footprint. The Intel® Xeon®
processor E5-1600 product family and the Intel® Xeon® processor E5-2600 product family are designed for Efficient Performance
server, workstation and HPC platforms. The Intel® Xeon® processor E5-4600 product family processor supports scalable server
and HPC platforms of two or more processors, including "glueless" 4-way platforms. Note: some processor features are not
available on all platforms.
These processors feature per socket, two Intel® QuickPath Interconnect point-to-point links capable of up to 8.0 GT/s, up to 40
lanes of PCI Express* 3.0 links capable of 8.0 GT/s, and 4 lanes of DMI2/PCI Express* 2.0 interface with a peak transfer rate of 5.0
GT/s. The processor supports up to 46 bits of physical address space and 48-bit of virtual address space.
Included in this family of processors is an integrated memory controller (IMC) and integrated I/O (IIO) (such as PCI Express* and
DMI2) on a single silicon die. This single die solution is known as a monolithic processor.
Each core supports two threads (Intel® Hyper-Threading Technology), up to 16
threads per socket
46-bit physical addressing and 48-bit virtual addressing
1 GB large page support for server applications
A 32-KB instruction and 32-KB data first-level cache (L1) for each core
A 256-KB shared instruction/data mid-level (L2) cache for each core
Up to 20 MB last level cache (LLC): up
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