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318589-005Quad-Core Intel® Xeon® Processor 5400 SeriesDatasheetAugust 2008

10solutions. Intel Virtualization Technology is used in conjunction with Virtual Machine Monitor software enabling multiple, independent software envi

Features1007.2.3 Stop-Grant StateWhen the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered no later than 20 bus clocks after

101FeaturesWhile in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor ret

Features102Enhanced Intel SpeedStep Technology creates processor performance states (P-states) or voltage/frequency operating points which are lower p

103Boxed Processor Specifications8 Boxed Processor Specifications8.1 IntroductionIntel boxed processors are intended for system integrators who build

Boxed Processor Specifications104Figure 8-1. Boxed Quad-Core Intel® Xeon® Processor 5400 Series1U Passive/3U+ Active Combination Heat Sink (With Remov

105Boxed Processor SpecificationsNotes:1. The heat sinks represented in these images are for reference only, and may not represent the final boxed pro

Boxed Processor Specifications106Figure 8-4. Top Side Board Keepout Zones (Part 1)

107Boxed Processor SpecificationsFigure 8-5. Top Side Board Keepout Zones (Part 2)

Boxed Processor Specifications108Figure 8-6. Bottom Side Board Keepout Zones

109Boxed Processor SpecificationsFigure 8-7. Board Mounting-Hole Keepout Zones

11Commonly used terms are explained here for clarification:• Quad-Core Intel® Xeon® Processor 5400 Series - Intel 64-bit microprocessor intended for d

Boxed Processor Specifications110Figure 8-8. Volumetric Height Keep-Ins

111Boxed Processor SpecificationsFigure 8-9. 4-Pin Fan Cable Connector (For Active CEK Heat Sink)

Boxed Processor Specifications112Figure 8-10. 4-Pin Base Board Fan Header (For Active CEK Heat Sink)

113Boxed Processor Specifications8.2.2 Boxed Processor Heat Sink Weight8.2.2.1 Thermal Solution WeightThe 1U passive/3U+ active combination heat sink

Boxed Processor Specifications114The fan power header on the baseboard must be positioned to allow the fan heat sink power cable to reach it. The fan

115Boxed Processor Specificationsaround the heatsink. It is assumed that a 40°C TLA is met. This requires a superior chassis design to limit the TRISE

Boxed Processor Specifications116§

117Debug Tools Specifications9 Debug Tools SpecificationsPlease refer to the appropriate platform design guidelines for information regarding debug to

Debug Tools Specifications1189.3.1 Mechanical ConsiderationsThe LAI is installed between the processor socket and the processor. The LAI plugs into th

12• Processor core – Processor core with integrated L1 cache. L2 cache and system bus interface are shared between the two cores on the die. All AC ti

13• VRM (Voltage Regulator Module) – DC-DC converter built onto a module that interfaces with a card edge socket and supplies the correct voltage and

14

15Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications2 Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications2.1 Fr

Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications162.2 Power and Ground LandsFor clean on-chip processor core power distribution,

17Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications2.4 Front Side Bus Clock (BCLK[1:0]) and Processor ClockingBCLK[1:0] directly

Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications182.4.2 PLL Power SupplyAn on-die PLL filter solution is implemented on the Quad

19Quad-Core Intel® Xeon® Processor 5400 Series Electrical SpecificationsThe Quad-Core Intel® Xeon® Processor 5400 Series provides the ability to opera

2 Quad-Core Intel® Xeon® Processor 5400 Series DatasheetINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRE

Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications20Notes:1. When the “111111” VID pattern is observed, the voltage regulator outp

21Quad-Core Intel® Xeon® Processor 5400 Series Electrical SpecificationsNote: The LL_ID[1:0] signals are used to select the correct loadline slope for

Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications22The TESTHI signals must use individual pull-up resistors as detailed below. A

23Quad-Core Intel® Xeon® Processor 5400 Series Electrical SpecificationsNotes:1. Refer to Chapter 5 for signal descriptions.2. These signals may be dr

Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications242.8 CMOS Asynchronous and Open Drain Asynchronous SignalsLegacy input signals

25Quad-Core Intel® Xeon® Processor 5400 Series Electrical SpecificationsNote:1. VTT supplies the PECI interface. PECI behavior does not affect VTT min

Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications262.11 Mixing ProcessorsIntel supports and validates dual processor configuratio

27Quad-Core Intel® Xeon® Processor 5400 Series Electrical SpecificationsNotes:1. For functional operation, all processor electrical, signal quality, m

Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications28Table 2-12. Voltage and Current Specifications (Sheet 1 of 2)Symbol Parameter

29Quad-Core Intel® Xeon® Processor 5400 Series Electrical SpecificationsNotes:1. Unless otherwise noted, all specifications in this table are based on

Quad-Core Intel® Xeon® Processor 5400 Series Datasheet 3Contents1Introduction...

Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications303. The voltage specification requirements are measured across the VCC_DIE_SENS

31Quad-Core Intel® Xeon® Processor 5400 Series Electrical SpecificationsNotes:1. Processor or Voltage Regulator thermal protection circuitry should no

Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications32Notes:1. Processor or Voltage Regulator thermal protection circuitry should no

33Quad-Core Intel® Xeon® Processor 5400 Series Electrical SpecificationsNotes:1. The VCC_MIN and VCC_MAX loadlines represent static and transient limi

Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications34Notes:1. The VCC_MIN and VCC_MAX loadlines represent static and transient limi

35Quad-Core Intel® Xeon® Processor 5400 Series Electrical SpecificationsFigure 2-7. Quad-Core Intel® Xeon® Processor X5482 VCC Static and Transient To

Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications36Figure 2-8. Quad-Core Intel® Xeon® Processor X5400 Series VCC Static and Trans

37Quad-Core Intel® Xeon® Processor 5400 Series Electrical SpecificationsNotes:1. The VCC_MIN and VCC_MAX loadlines represent static and transient limi

Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications38Notes:1. Unless otherwise noted, all specifications in this table apply to all

39Quad-Core Intel® Xeon® Processor 5400 Series Electrical SpecificationsNotes:1. VOS is the measured overshoot voltage.2. TOS is the measured time dur

4 Quad-Core Intel® Xeon® Processor 5400 Series Datasheet6.2.1 Intel® Thermal Monitor Features...

Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications40The AGTL+ reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID

41Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications7. Threshold Region is defined as a region entered around the crossing point v

Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications42§Figure 2-14. Differential Clock Crosspoint SpecificationFigure 2-15. Differen

43Mechanical Specifications3 Mechanical SpecificationsThe Quad-Core Intel® Xeon® Processor 5400 Series is packaged in a Flip Chip Land Grid Array (FC-

Mechanical Specifications44Note: Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solut

45Mechanical SpecificationsFigure 3-3. Quad-Core Intel® Xeon® Processor 5400 Series Package Drawing (Sheet 2 of 3)

Mechanical Specifications46Note: The optional dimple packing marking highlighted by Detail F from the above drawing may only be found on initial proce

47Mechanical Specifications3.2 Processor Component Keepout ZonesThe processor may contain components on the substrate that define component keepout zo

Mechanical Specifications483.4 Package Handling GuidelinesTable 3-2 includes a list of guidelines on a package handling in terms of recommended maximu

49Mechanical SpecificationsNote: 2D matrix is required for engineering samples only (encoded with ATPO-S/N).3.9 Processor Land CoordinatesFigure 3-6 a

Quad-Core Intel® Xeon® Processor 5400 Series Datasheet 5Figures2-1 Input Device Hysteresis ...

Mechanical Specifications50§Figure 3-7. Processor Land Coordinates, Bottom ViewVTT/ Clocks1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930

51Land Listing4 Land Listing4.1 Quad-Core Intel® Xeon® Processor 5400 Series Pin AssignmentsThis section provides sorted land list in Table 4-1 and Ta

Land Listing52BSEL0 G29 CMOS ASync OutputBSEL1 H30 CMOS ASync OutputBSEL2 G30 CMOS Async OutputCOMP0 A13 Power/Other InputCOMP1 T1 Power/Other InputCO

53Land ListingDP2# H16 Common Clk Input/OutputDP3# J17 Common Clk Input/OutputDRDY# C1 Common Clk Input/OutputDSTBN0# C8 Source Sync Input/OutputDSTBN

Land Listing54RESERVED G24RESERVED F24RESERVED F26RESERVED F25RESERVED G25RESERVED W3RESERVED AM2RESET# G23 Common Clk InputRS0# B3 Common Clk InputRS

55Land ListingVCC AG30 Power/OtherVCC AG8 Power/OtherVCC AG9 Power/OtherVCC AH11 Power/OtherVCC AH12 Power/OtherVCC AH14 Power/OtherVCC AH15 Power/Oth

Land Listing56VCC AN8 Power/OtherVCC AN9 Power/OtherVCC J10 Power/OtherVCC J11 Power/OtherVCC J12 Power/OtherVCC J13 Power/OtherVCC J14 Power/OtherVCC

57Land ListingVCC W8 Power/OtherVCC Y23 Power/OtherVCC Y24 Power/OtherVCC Y25 Power/OtherVCC Y26 Power/OtherVCC Y27 Power/OtherVCC Y28 Power/OtherVCC

Land Listing58VSS AF29 Power/Other VSS AF3 Power/Other VSS AF30 Power/Other VSS AF6 Power/Other VSS AG10 Power/OtherVSS AG13 Power/OtherVSS AG16 P

59Land ListingVSS B11 Power/Other VSS B14 Power/Other VSS B17 Power/Other VSS B20 Power/Other VSS B24 Power/Other VSS B5 Power/Other VSS B8 Powe

6 Quad-Core Intel® Xeon® Processor 5400 Series DatasheetTables1-1 Quad-Core Intel® Xeon® Processor 5400 Series ...

Land Listing60VSS L7 Power/Other VSS M1 Power/Other VSS M7 Power/Other VSS N3 Power/Other VSS N6 Power/Other VSS N7 Power/Other VSS P23 Power/Ot

61Land Listing4.1.2 Land Listing by Land NumberTable 4-2. Land Listing by Land Number (Sheet 1 of 20)Pin No. Pin NameSignal Buffer TypeDirectionA10 D0

Land Listing62AD26 VCC Power/OtherAD27 VCC Power/OtherAD28 VCC Power/OtherAD29 VCC Power/OtherAD3 BINIT# Common Clk Input/OutputAD30 VCC Power/OtherAD

63Land ListingAG18 VCC Power/OtherAG19 VCC Power/OtherAG2 BPM3# Common Clk Input/OutputAG20 VSS Power/OtherAG21 VCC Power/OtherAG22 VCC Power/OtherAG2

Land Listing64AJ9 VCC Power/OtherAK1 RESERVEDAK10 VSS Power/OtherAK11 VCC Power/OtherAK12 VCC Power/OtherAK13 VSS Power/OtherAK14 VCC Power/OtherAK15

65Land ListingAM26 VCC Power/OtherAM27 VSS Power/OtherAM28 VSS Power/OtherAM29 VCC Power/OtherAM3 VID2 CMOS Async OutputAM30 VCC Power/OtherAM4 VSS Po

Land Listing66C2 BNR# Common Clk Input/OutputC20 DBI3# Source Sync Input/OutputC21 D58# Source Sync Input/OutputC22 VSS Power/OtherC23 RESERVEDC24 VSS

67Land ListingF10 VSS Power/OtherF11 D23# Source Sync Input/OutputF12 D24# Source Sync Input/OutputF13 VSS Power/OtherF14 D28# Source Sync Input/Outpu

Land Listing68H27 VSS Power/OtherH28 VSS Power/OtherH29 VSS Power/OtherH3 VSS Power/OtherH30 BSEL1 CMOS Async OutputH4 RSP# Common Clk InputH5 BR1# Co

69Land ListingM28 VCC Power/OtherM29 VCC Power/OtherM3 STPCLK# CMOS Async InputM30 VCC Power/OtherM4 A07# Source Sync Input/OutputM5 A03# Source Sync

Quad-Core Intel® Xeon® Processor 5400 Series Datasheet 7Revision History§Revision Description Date001 Initial release November 2007002Added product in

Land Listing70§U28 VCC Power/OtherU29 VCC Power/OtherU3 AP1# Common Clk Input/OutputU30 VCC Power/OtherU4 A13# Source Sync Input/OutputU5 A12# Source

71Signal Definitions5 Signal Definitions5.1 Signal DefinitionsTable 5-1. Signal Definitions (Sheet 1 of 8)Name Type Description NotesA[37:3]# I/O A[37

Signal Definitions72BCLK[1:0] I The differential bus clock pair BCLK[1:0] (Bus Clock) determines the FSB frequency. All processor FSB agents must rece

73Signal DefinitionsBSEL[2:0] O The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the processor input clock frequency. Table 2-2 def

Signal Definitions74DEFER# I DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFE

75Signal DefinitionsGTLREF_DATA_MIDGTLREF_DATA_ENDI GTLREF_DATA determines the signal reference level for AGTL+ data input lands. GTLREF_DATA is used

Signal Definitions76MCERR# I/O MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without a bus protocol violation. It may be

77Signal DefinitionsRSP# I RSP# (Response Parity) is driven by the response agent (the agent responsible for completion of the current transaction) du

Signal Definitions78Notes:1. For this processor land on the Quad-Core Intel® Xeon® Processor 5400 Series, the maximum number of symmetric agents is on

79Thermal Specifications6 Thermal Specifications6.1 Package Thermal SpecificationsThe Quad-Core Intel® Xeon® Processor 5400 Series requires a thermal

8 Quad-Core Intel® Xeon® Processor 5400 Series Datasheet

Thermal Specifications80Processor Thermal Features). Systems that implement fan speed control must be designed to use this data. Systems that do not a

81Thermal Specificationspower dissipation is currently planned. Intel® Thermal Monitor 1 and Intel® Thermal Monitor 2 feature must be enabled for the

Thermal Specifications82Table 6-2. Quad-Core Intel® Xeon® Processor X5492 and X5482 (C-step)Thermal Profile TablePower (W) TCASE_MAX (°C)0 35.05 35.91

83Thermal SpecificationsNotes:1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor

Thermal Specifications84Table 6-4. Quad-Core Intel® Xeon® Processor X5400 Series Thermal Profile A TablePower (W) TCASE_MAX (°C)0 42.85 43.610 44.515

85Thermal SpecificationsNotes:1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor

Thermal Specifications86Notes:1. Please refer to Table 6-7 for discrete points that constitute the thermal profile.2. Implementation of the Quad-Core

87Thermal SpecificationsNotes:1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor

Thermal Specifications88Notes:1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor

89Thermal SpecificationsNotes:1. Please refer to Table 6-11 for discrete points that constitute the thermal profile.2. Implementation of the Quad-Core

91 IntroductionThe Quad-Core Intel® Xeon® Processor 5400 Series is a server/workstation processor utilizing four 45-nm Hi-k next generation Intel® Cor

Thermal Specifications906.1.2 Thermal MetrologyThe minimum and maximum case temperatures (TCASE) are specified in Table 6-2, Table 6-4, Table 6-5, and

91Thermal Specificationsneeded by modulating (starting and stopping) the internal processor core clocks. The temperature at which the Intel® Thermal M

Thermal Specifications92The second operating point consists of both a lower operating frequency and voltage. The lowest operating frequency is determi

93Thermal SpecificationsSeries must not rely on software usage of this mechanism to limit the processor temperature. If bit 4 of the IA32_CLOCK_MODULA

Thermal Specifications946.2.5 THERMTRIP# SignalRegardless of whether or not Intel® Thermal Monitor 1 or Intel® Thermal Monitor 2 is enabled, in the ev

95Thermal Specificationsshould utilize the relative temperature value delivered over PECI in conjunction with the TCONTROL MSR value to control or opt

Thermal Specifications966.3.2 PECI Specifications6.3.2.1 PECI Device AddressThe PECI device address for socket 0 is 0x30 and socket 1 is 0x31. Please

97Features7 Features7.1 Power-On Configuration OptionsSeveral configuration options can be configured by hardware. The Quad-Core Intel® Xeon® Processo

Features987.2.1 Normal StateThis is the normal operating state for the processor.7.2.2 HALT or Extended HALT StateThe Extended HALT state (C1E) is ena

99FeaturesNotes:1. Processors running in the lowest bus ratio supported as shown in Table 2-1, will enter the HALT State when the processor has execut